Field of the Disclosure
The present disclosure relates generally to computing systems and, more particularly, to power management in computing systems.
Description of the Related Art
Computing systems often utilize power-saving techniques in which the state of a processing component is temporarily saved to memory and the processing component is then placed in a low power state while in an idle mode. When the processing component exits the idle mode to return to an active mode, the saved state is accessed from the memory and used to restore the processing component to its previous state before entering the idle mode. However, when the processing component enters the idle mode, one or more caches associated with the processing component typically are flushed to a cache level or memory outside of the power domain of the processing component, and the flushed cache is then placed in a low power state in which the cache cannot reliably retain data. As such, when the processing component exits the idle mode, the cache is empty of valid data and the processing component suffers a “cold start” penalty because the initial memory accesses performed after the exit from the idle mode result in cache misses and thus must be serviced by memory or a higher level of cache. As memory accesses to memory or higher level caches exhibit higher latency than accesses to lower levels of cache, this cold start penalty can introduce significant performance losses.